1. Field of the Invention
The present invention relates to an insulated gate field-effect transistor. More particularly, the present invention relates to an insulated gate field-effect transistor in which a short-channel effect is suppressed.
2. Description of the Related Art
The insulated-gate field-effect transistor has been mainly used for semiconductor integrated circuits. Recently, there has been a demand for a smaller and faster insulated-gate field-effect transistor. Accordingly, the transistor device has been miniaturized. However, when the miniaturization of the transistor device is accompanied by a shortened channel length, the short-channel effect may result. That is, as the transistor device is miniaturized, the ratio of the gate depletion layer charge to the total depletion layer charge is accordingly reduced, thereby causing problems such as lowering of the threshold voltage, deterioration of the subthreshold performance, or generation of a punchthrough.
Particularly, in an nMOS transistor, when crystal defects are generated in the impurity implanted region while forming a source-drain region (high concentration impurity region) by implanting arsenic .sup.75 As.sup.+ as an n-type impurity into a p-type substrate at a high concentration, boron .sup.11 B.sup.+ contained in the p-type substrate in the vicinity of the source-drain region is segregated in the crystal defects. As a result, in the vicinity of an n.sup.+ /p junction of the source-drain region, the concentration of B as a p-type impurity is reduced (i.e., the B-depletion phenomenon occurs). The depletion layer at the source-drain junction becomes larger due to the B-depletion phenomenon, whereby the short-channel effect may occur more easily. A commonly-employed method to avoid this effect is to increase the B concentration in the substrate in such a manner that the high concentration region surrounds an LDD (Lightly Doped Drain) region.
Hereinafter, a method for producing a conventional nMOS transistor will be described with reference to FIGS. 9A to 9H. FIGS. 9A to 9H are cross-sectional views illustrating the method for producing the conventional nMOS transistor.
First, as illustrated in FIG. 9A, a p well 92, a device separation film 93, and a gate insulating film 94 are formed on a silicon-substrate 91. Thereafter, a gate electrode 95 is formed by depositing polycrystalline silicon and then photo-etching the deposited layer.
Next, as illustrated in FIG. 9B, a thin insulating film 96 is formed by deposition so as to entirely cover the surface of the substrate. Then, an n-type LDD region 97 is formed by ion implantation of the .sup.75 As.sup.+ ion, for example, as an n-type impurity.
Subsequently, as illustrated in FIG. 9C, .sup.11 B.sup.+ as a p-type impurity is implanted at a large oblique angle of about 20 to 60.degree.. Thus, a p-type semiconductor region 98 is formed surrounding the n-type LDD region 97. The resulting p-type semiconductor region 98 has the same conductive type as that of the p well 92 (or the substrate 91) and has an increased p-type impurity concentration.
Then, as illustrated in FIG. 9D, a thick insulating film 99 is formed to be about 150 nm in thickness. Thereafter, as illustrated in FIG. 9E, a sidewall oxide film 100 is formed on each sidewall of the gate electrode 95 by anisotropic etching.
Moreover, as illustrated in FIG. 9F, the .sup.75 As.sup.+ ion is implanted at a concentration (e.g., about 3.times.10.sup.15 cm.sup.-2 at an energy of about 80 keV) greater than that of the n-type impurity (.sup.75 As.sup.+) ion implantation for forming the LDD region 97. Thus, a source-drain region 101 as an n-type impurity region is formed while the gate electrode 95 is doped to be n.sup.+.
Then, as illustrated in FIG. 9G, an annealing process is performed in order to activate the LDD region 97, the source-drain region 101 and the gate electrode 95 and to restore the crystal defects. In this step, an annealing process for 10 minutes at about 850.degree. C. in a nitrogen atmosphere, an RTA (Rapid thermal annealing) process for 20 seconds at about 1000.degree. C., or the like, may be performed.
Then, as illustrated in FIG. 9H, a high melting point metal film is deposited by sputtering, which is then thermally processed by a 2-step RTA process, thus forming silicide portions 102a and 102b in a self-alignment manner. The insulated-gate field-effect transistor is thus produced.
According to the above-described method, the p-type semiconductor region 98 having an increased p-type impurity concentration is formed surrounding the n-type LDD region 97 by implanting an impurity of the same conductive type (i.e., p-type: this conductive type will be referred to as the "first conductive type") as that of the p well 92 (i.e., the channel region). This, however, may cause the following problems.
Since the LDD region 97 is surrounded by the p-type semiconductor region 98, in which the p-type impurity concentration is increased, the electric field near the drain region is particularly intensified, thereby lowering the hot carrier resistance.
Moreover, as the channel length is shortened, the influence of the p-type high concentration impurity in the p-type semiconductor region 98 on the high concentration impurity region in the channel region accordingly increases. Thus, a reverse short-channel effect occurs, i.e., the threshold voltage of the channel region increases.
Furthermore, boron .sup.11 B.sup.+, which is implanted as a p-type impurity, diffuses faster than arsenic .sup.75 As.sup.+, which is implanted as an n-type impurity for forming the source-drain region 101. Therefore, a region having a high boron concentration is formed beneath the source-drain region 101, thereby increasing the source-drain junction capacitance. This lowers the operation speed of the circuit and increases the power consumption while the driving power is lowered due to the mobility deterioration.